1. Field of the Invention
The present invention relates to a semiconductor memory device for controlling refresh operation for a memory cell array in normal operation, and particularly relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory) in which the memory cell array is divided into a plurality of banks and the refresh operation can be performed by selecting a plurality of word lines for each bank.
2. Description of the Related Art
Generally, refresh operation should be performed with a predetermined refresh period in order to hold data in a memory cell array of DRAM. In normal operation of DRAM, a row address is counted up by a refresh counter at every refresh interval specified in a specification, and the refresh operation is sequentially performed for the row address indicated by a count value. DRAM is generally divided into a plurality of banks and refresh operation is performed for each bank at the same time. For example, considering a case in which the refresh operation is performed for one of 2m word lines each corresponding to a m-bit row address at every refresh interval in each bank, the refresh period of each memory cell is 2m·t (t: refresh interval). However, an increase in storage capacity of DRAM likely makes it difficult to ensure data retention characteristics of the memory cell in the refresh period 2m·t. Therefore, it is desirable to ensure a refresh period conforming to an actual value of the data retention time of the memory cell by increasing the frequency of refresh operations.
As a measure against the problem, a configuration is employed in which a plurality of word lines is refreshed at the same time at every refresh interval in each bank (For example, see Japanese Patent Laid-Open No. 2003-187578). For example, one bit of the row address is set to a “don't care” state so that the bit becomes irrelevant (regardless of whether it is 0 or 1), and corresponding two word lines are selected to be refreshed, which can be refreshed at the same time. The count value of the refresh counter is assigned to each bit included in an (m−1) bit row address except the irrelevant bit, and is counted up sequentially so as to be supplied to each bank. Thereby, refresh operations may be performed 2m-1 times to complete refreshing all of 2m word lines which can be designated by an in-bit row address, and thus the refresh period in this case is reduced by half.
In the above conventional configuration of DRAM, the number of word lines to be refreshed at every refresh interval is increased from one to two, and it is possible to reduce the refresh period by half. However, when reducing the refresh period by half, a situation is assumed in which the refresh period becomes too short for the actual value of the data retention time of the memory cell while the refresh period actually should have been slightly reduced. In other words, the refresh operation for one word line at every refresh interval is insufficient in terms of the data retention characteristics of the memory cell, while the refresh operation for two word lines at every refresh interval is too frequent and extra current is consumed. If the actual value of the data retention time of the memory cell corresponds to an average number of about 1.5 word lines at every refresh interval, it is difficult to adjust the refresh period so as to conform to the average number, thus it is a problem that current is unnecessarily consumed during the refresh operation.
Further, as a measure for appropriately adjusting the refresh period, one word line can be refreshed for each bank in a certain time zone, while two word lines can be refreshed for each bank in the other time zone. Such a measure can reduce average current in the refresh operation of DRAM in accordance with the refresh period, however cannot reduce peak current. That is, the peak current of DRAM is specified by current flowing at a timing to refresh two word lines at the same time in each bank. Thus, it is a problem that reliability of the refresh operation of DRAM is lowered by noise due to the peak current. Further, it is also a problem that circuit scale of a boost circuit and the like for driving the word line is required to be larger in accordance with the peak current.